A Digitaly Programmable Switched Current Analog Delay Line

High performance analog building blocks are of great importance in mixed-mode ASIC´s. The switched current approach allows their realization in purely digital processes. An analog programmable delay line fabricated in a standard digital CMOS process is presented. It uses an enhanced current memory cell and achieves more than 40dB of signal to (noise+distorsion) ratio at sampling frequencies up to 50 MHz with only 57 mW power dissipation.