Pseudo-Complementary FET Logic : a Low-Power logic family in GaAs

This paper describes an efficient low-power static logic family in GaAs. Its behaviour mimics the one of CMOS, by compensating the lack of complementary transistors by the use of complementary logic signals. This Pseudo-Complementary FET Logic (PCFL) is fully compatible with Direct Coupled FET Logic. An original bootstrapping technique compensates the level degradation due to the use of enhancement-mode MESFETs only. The power consumption of an inverter is of the order of 10¿W at 100MHz. Preliminary measurement results on an inverter chain are reported.