Title :
12 Bit-1mW ΣΔ-Modulator for 2.4V supply voltage
Author :
Sauerbrey, J. ; Mauthe, M.
Author_Institution :
SIEMENS AG, ZFE T ME 2, Otto-Hahn-Ring 6, 81730 Mÿnchen, Germany, e-mail: jens@parl.zfe.siemens.de
Abstract :
A 3rd order low-power, low-voltage single loop ΣΔ-ADC designed for speech signals is presented. The integrators were scaled to have a maximum output swing of IV, so that the converter could operate for supply voltages between 2.3V and 2.6V. The ΣΔ-ADC was implemented in an standard 1.5 μm n-well CMOS process. 1mW power dissipation for 70dB S/(N+D) performance in a 16kHz bandwidth is obtained.
Keywords :
Bandwidth; CMOS process; Chebyshev approximation; Frequency conversion; Poles and zeros; Signal design; Signal to noise ratio; Speech; Stability; Voltage;
Conference_Titel :
Solid-State Circuits Conference, 1995. ESSCIRC '95. Twenty-first European
Conference_Location :
Lille, France
Print_ISBN :
2-86332-180-3
