A Portable Clock Multiplier Generator using Digital CMOS Standard Cells

This paper presents a circuit fabricated to test a new method of clock frequency multiplication. This new approach uses a digital CMOS process in order to implement the delay locked loop. This multiplier does not require external components. Moreover it is generated by a parameterized generator written in C which relies on a portable digital standard cell library, for automatic place and route. In 1¿m CMOS process a 170Mhz clock signal has been obtained from a 8.5Mhz external clock with a measured jitter lower than 300ps.