Design Considerations for Tapered CMOS Inverter Chains with Improved Hot-Carrier Reliability

The hot-carrier induced degradation of the transient circuit performance in cascaded CMOS digital circuit structures is investigated and the degradation of tapered (scaled) inverter chains is modeled. It is shown that for a wide class of circuits, the performance degradation due to dynamic hot-carrier effects can be expressed as a function of the nMOS and pMOS transistor channel widths, and the output load capacitance. A simple design guideline based on the scaling factor (F) and the transistor aspect ratio (r) is presented for the improvement of long-term reliability in scaled buffer structures with respect to hot-carrier induced device aging.