Title :
A Fast 16 Bit NMOS Parallel Multiplier
Author :
Lerouge, C. ; Girard, P. ; Colardelle, J. ; Obermeier, C.
Author_Institution :
Laboratoire Central de Télécommunications, Vélizy, France
Abstract :
A fast (120ns) and low power (200 mW) NMOS multiplier is described. It contains a non-technology dependent 16 × 16 parallel array. Silicon area is 5 mm2.
Keywords :
Adders; Array signal processing; Delay effects; Integrated circuit interconnections; Logic; MOS devices; Propagation delay; Signal design; Silicon; Tellurium;
Conference_Titel :
Solid-State Circuits Conference, 1983. ESSCIRC '83. Ninth European
Conference_Location :
Lausanne, Switzerland
Print_ISBN :
2-88074-021-5
