Correction for call for papers: IEEE Transactions for Electron Devices “ Variation aware technology and circuit co design”

The special issue on "Variation aware technology and circuit co design" is devoted to the research and development activities on variation aware process/device technology and co-optimization with circuit design. Rapid pace of new technology introduction to CMOS technology requires much more sophisticate optimization of process, device, and circuit design, in order to maximize return on investment. Careful optimization of process technology, device structure, layout and circuit design in holistic manner enables significant performance improvement while reducing overall power consumption with least amount of area penalty. Among many challenges for this holistic optimization, higher process and device variation becomes one of most critical issues as process technology is marching into below 20nm node. New material technology and non-planar device structure add additional variation source on top of conventional geometrical effect. Not only reducing extrinsic portion of variation is important, understanding the effect of such variation in various actual circuit design is also very important. In addition to addressing variation at individual process and design element, this special edition also touches on the impact of variation aware optimization to overall SOC design that requires both high performance and low power functional blocks. Submission Deadline: October 31, 2014 Scheduled Publication Date: June 2015.