• DocumentCode
    518307
  • Title

    An improvement algorithm to runahead execution

  • Author

    Liu, De-feng

  • Author_Institution
    Sch. of Comput., Nat. Univ. of Defense Technol., Changsha, China
  • Volume
    1
  • fYear
    2010
  • fDate
    16-18 April 2010
  • Abstract
    Runahead execution can significantly improve the memory-level parallelism, and processor needn´t be modified a lot. But Runahead execution processor excute more instructions than traditional processor, even triple the number of instructions of the common execution, So it severely increases processors´ power waste. After analyzing, we find there are many useless instructions executed when Runahead processor is in runahead´s execting stage, We present a new algorithm to reduce the useless instructions. The results of the Experimention show that this improvement algorithm mostly can reduce 50% useless instructions in runahead execution processor´s pre-excute stage, and basically don´t affect the performance a lot.
  • Keywords
    instruction sets; microprocessor chips; memory-level parallelism; microprocessor; runahead execution processor; Algorithm design and analysis; Computer aided instruction; Concurrent computing; Costs; Delay; Hardware; Microprocessors; Out of order; Parallel processing; Prefetching; Runahead execution; cache miss; checkpoint; memory-level parallelism;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Computer Engineering and Technology (ICCET), 2010 2nd International Conference on
  • Conference_Location
    Chengdu
  • Print_ISBN
    978-1-4244-6347-3
  • Type

    conf

  • DOI
    10.1109/ICCET.2010.5486007
  • Filename
    5486007