An Interleaving Switch-based Crossbar Architecture for MP SoC on FPGA

The communication mechanisms employed in systems on a single chip(SoC) are an important contribution to their overall performance. To date, bus-based paradigm is applied in many areas of real-time applications of SoCs realizing on FPGA due to its flexibility and simplification in designing tool. Although offering the module-increasing flexibility, its bandwidth and scalability still become problem. To alleviate these problems, switch-based paradigm has been introduced to improve the above three important factors. In addition, its changeable communication-pattern property depending on various applications at run-time is advantageous. Thus, the possibility of multiple applications running on single platform can be achieved. Nevertheless, many-to-one (gathering) functionality based on the switch-based paradigm has disadvantage at output delay. In this paper, interleaving mechanism is introduced to solve this problem. Moreover, 6x6 interleaving switch-based crossbar architecture along the proposed mechanism is implemented and verified on Xilinx FPGA Virtex2P XC2VP30. Verifying its performance with 256-word samples at 100 MHz and measuring the gathered output data by logic analyzer, the maximum bandwidth while all Source Nodes multicast to a Destination Node is 741.32 Mbit/sec, and 533 Mbit/sec unicasting data. Flip-Flop and LUTs are 3.33% and 16.05% of the target FPGA; likewise, estimation frequency respond is 113.854 MHz obtained from the Xilinx ISE tool.