DocumentCode :
523041
Title :
Analysis of dynamic voltage/frequency scaling in chip-multiprocessors
Author :
Herbert, Steven ; Marculescu, Diana
Author_Institution :
Electr. & Comput. Eng., Carnegie Mellon Univ., Pittsburgh, PA, USA
fYear :
2007
fDate :
27-29 Aug. 2007
Firstpage :
38
Lastpage :
43
Abstract :
Fine-grained dynamic voltage/frequency scaling (DVFS) demonstrates great promise for improving the energy-efficiency of chip-multiprocessors (CMPs), which have emerged as a popular way for designers to exploit growing transistor budgets. We examine the tradeoffs involved in the choice of both DVFS control scheme and method by which the processor is partitioned into voltage/frequency islands (VFIs). We simulate real multithreaded commercial and scientific workloads, demonstrating the large real-world potential of DVFS for CMPs. Contrary to the conventional wisdom, we find that the benefits of per-core DVFS are not necessarily large enough to overcome the complexity of having many independent VFIs per chip.
Keywords :
microprocessor chips; multi-threading; multiprocessing systems; power aware computing; power utilisation; DVFS control scheme; chip multiprocessor; dynamic voltage frequency scaling; multithreaded workload; transistor budget; voltage frequency island; Algorithm design and analysis; Costs; Design engineering; Dynamic voltage scaling; Energy efficiency; Frequency; Optimization methods; Permission; Power engineering and energy; Voltage control; chip-multiprocessor; dynamic voltage/frequency scaling;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Low Power Electronics and Design (ISLPED), 2007 ACM/IEEE International Symposium on
Conference_Location :
Portland, OR
Electronic_ISBN :
978-1-59593-709-4
Type :
conf
DOI :
10.1145/1283780.1283790
Filename :
5514266
Link To Document :
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