On the selection of arithmetic unit structure in voltage overscaled soft digital signal processing

Author

Yang Liu ; Tong Zhang

Author_Institution

Electr., Comput., & Syst. Eng. Dept., Rensselaer Polytech. Inst., Troy, NY, USA

fYear

2007

fDate

27-29 Aug. 2007

Firstpage

250

Lastpage

255

Abstract

A soft digital signal processing (DSP) design paradigm has been recently proposed to reduce the energy consumption of DSP systems through voltage overscaling. This paper shows that the selection of arithmetic unit structure can be an important and non-trivial issue in soft DSP system design. We present an optimal formulation and propose sub-optimal low-complexity approximations for selecting the appropriate arithmetic unit structure in voltage overscaled signal processing systems. We further present a case study on choosing the appropriate MAC (multiply-accumulate) structure in voltage overscaled FIR (finite impulse response) filter.

Keywords

FIR filters; computational complexity; digital signal processing chips; power aware computing; arithmetic unit structure; energy consumption; finite impulse response filter; multiply-accumulate structure; soft digital signal processing design paradigm; sub-optimal low-complexity approximations; voltage overscaling; Costs; Degradation; Digital arithmetic; Digital signal processing; Energy consumption; Finite impulse response filter; Signal design; Signal processing; Signal processing algorithms; Voltage; low power; signal processing; voltage overscaling;

fLanguage

English

Publisher

ieee

Conference_Titel

Low Power Electronics and Design (ISLPED), 2007 ACM/IEEE International Symposium on

Conference_Location

Portland, OR

Electronic_ISBN

978-1-59593-709-4

Type

conf

DOI

10.1145/1283780.1283834

Filename

5514327