Fault injection technique approach for testbench analysis

As the chips complexity continues to grow, the importance of functional verification in the design flow increased, together with the time consumed for developing the verification environment and verifying the design. Creating reliable environments and reduced time for their debug increase the verification productivity. Verification environments have complex testbenches surrounding the digital design but these testbenches often contain undetected errors. This paper describes the usage of fault-injection technique applied to SystemVerilog language constructs used in testbenches, to identify such hidden errors. The testbench implementation can be analyzed using fault-injection techniques, leading to a better overview of its functionality and improving the design verification process. Possible faults to be injected by altering language constructs are presented, highlighting their impact on simulation results an how they can be used to detect potential testbench problems.