• DocumentCode
    524004
  • Title

    Networks on Chips: From research to products

  • Author

    De Micheli, G. ; Seiculescu, C. ; Murali, S. ; Benini, L. ; Angiolini, F. ; Pullini, A.

  • Author_Institution
    LSI, EPFL, Lausanne, Switzerland
  • fYear
    2010
  • fDate
    13-18 June 2010
  • Firstpage
    300
  • Lastpage
    305
  • Abstract
    Research on Networks on Chips (NoCs) has spanned over a decade and its results are now visible in some products. Thus the seminal idea of using networking technology to address the chip-level interconnect problem has been shown to be correct. Moreover, as technology scales down in geometry and chips scale up in complexity, NoCs become the essential element to achieve the desired levels of performance and quality of service while curbing power consumption levels. Design and timing closure can only be achieved by a sophisticated set of tools that address NoC synthesis, optimization and validation.
  • Keywords
    integrated circuit design; integrated circuit interconnections; network-on-chip; NoC synthesis; chip-level interconnect problem; network on chips; networking technology; power consumption level curbing; quality of service; Communication system traffic control; Delay estimation; Energy consumption; Field programmable gate arrays; Network-on-a-chip; Power system interconnection; System performance; System-on-a-chip; Timing; Wires; Network on Chip; NoC; SoC; System on Chip;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Design Automation Conference (DAC), 2010 47th ACM/IEEE
  • Conference_Location
    Anaheim, CA
  • ISSN
    0738-100X
  • Print_ISBN
    978-1-4244-6677-1
  • Type

    conf

  • Filename
    5523566