A study of p stopper effect on 30V-gate/80V-dram bi-directional NMOSFET and 80V ESD protection BJT

This paper describes the impact of the introduction of a p stopper to a 30V-gate bi-directional NMOSFET and an ESD protection BJT fabricated using our 80V-class HV-MOS process. We found that the p stopper that selectively formed below the channel region of the NMOSFET not only helped to prevent the S-D punch-through but also caused some important effects: (i) alleviated the electric field crowding without sacrificing the optimized resurf breakdown voltages at high drain bias, and (ii) intensified the crowding near the channel surface with increasing the channel length at a high common-G/S/D bias. We confirmed that the former effect improved both the current and the on/off-breakdown performance while the latter did not decrease the usable source bias, which equals the rated gate voltage of 30V. The p stopper applied to the core base edge of the BJT also made some snapback current evade from flowing near the surface, which increased the secondary breakdown current by over 30%. These p stoppers did not require an extra mask step in our 80V-MOS process.