Comparison of two data hazard handling schemes for asynchronous pipelined processors

Since asynchronous logic adopts a distributed control scheme, the traditional methods for handling hazards in synchronous processors cannot be directly applied to asynchronous processors. Recently, the data hazard detection table (DHDT) scheme has been regarded as an effective method for handling data hazards in asynchronous processors. In this paper, two asynchronous data hazard handling schemes, the DHDT scheme and the proposed destination register chain (DRC) scheme, are compared in terms of performance and hardware complexity. In order to evaluate these two data hazard handling schemes, we have used the Balsa asynchronous synthesis system to implement two asynchronous pipelined processors, AsynRISC-DHDT and AsynRISC-DRC, which employ DHDT and DRC, respectively, to deal with data hazards. Experimental results show that AsynRISC-DRC can achieve a 13% reduction in hardware area cost and a performance gain of 22.1% compared with AsynRISC-DHDT.