The efficient sample rate conversion architecture in digital IF receiver

The wideband signal is sampled at a high rate in digital IF(intermediate frequencies) receiver using a fixed master clock. After extracting individual narrowband channels from wideband signal, the sample rate is much higher than single channel bandwidth. It is necessary to resample the signal with a lower rate to reduce data redundancy. And the receiver should has the capability of operating in all sorts of communication standard. So sensitive SRC(sample rate conversion) is necessary in the receiver. The paper proposed an efficient SRC architecture and an optimized algorithm for assigning changing rate factor. The architecture is programmable, hardware sharing, with lower power consumption, which take advantage of renewed comb filters to improve alias rejection and reduce power consumption of the decimation at high rate. The optimized algorithm is flexible and simple. It can realize SRC efficiently by optimum composition of algorithm and architecture.