DocumentCode :
526500
Title :
A transceiver-aware routing framework for on-chip nanophotonic integration
Author :
Chen, Xiaodao ; Hu, Shiyan
Author_Institution :
Dept. of Electr. & Comput. Eng., Michigan Technol. Univ., Houghton, MI, USA
fYear :
2010
fDate :
13-15 Aug. 2010
Firstpage :
595
Lastpage :
600
Abstract :
A variety of issues such as increasing interconnect resistivity, low bandwidth and serious cross talks have limited the usage of copper interconnect in the deep submicrometer node. On-chip optical waveguide emerges as a promising replacement material for copper interconnect. The deployment of on-chip optical integration in modern VLSI design certainly needs the advanced CAD tools. This work proposes a novel transceiver-aware tree construction algorithm for on-chip optical waveguide routing. The new algorithm is dedicated to on-chip nanophotonic integration which features the optimization of curved routing and nanophotonic energy loss. Experimental results on 500 timing critical nets demonstrate the effectiveness and the efficiency of our techniques. The transceiver-aware on-chip optical tree construction algorithm can reduce the energy demand by 2.1× compared to a natural minimum spanning tree heuristic. Our constructed optical trees can improve the timing by about 2× compared to copper trees.
Keywords :
integrated optics; nanophotonics; network routing; optical interconnections; optical waveguides; transceivers; VLSI design; on-chip nanophotonic integration; on-chip optical integration; on-chip optical waveguide routing; transceiver aware routing framework; transceiver aware tree construction algorithm; Delay; Logic gates; Modulation; Optical amplifiers; Optical coupling; Optical waveguides; Photonics;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Intelligent Control and Information Processing (ICICIP), 2010 International Conference on
Conference_Location :
Dalian
Print_ISBN :
978-1-4244-7047-1
Type :
conf
DOI :
10.1109/ICICIP.2010.5564165
Filename :
5564165
Link To Document :
بازگشت