A transceiver-aware routing framework for on-chip nanophotonic integration

A variety of issues such as increasing interconnect resistivity, low bandwidth and serious cross talks have limited the usage of copper interconnect in the deep submicrometer node. On-chip optical waveguide emerges as a promising replacement material for copper interconnect. The deployment of on-chip optical integration in modern VLSI design certainly needs the advanced CAD tools. This work proposes a novel transceiver-aware tree construction algorithm for on-chip optical waveguide routing. The new algorithm is dedicated to on-chip nanophotonic integration which features the optimization of curved routing and nanophotonic energy loss. Experimental results on 500 timing critical nets demonstrate the effectiveness and the efficiency of our techniques. The transceiver-aware on-chip optical tree construction algorithm can reduce the energy demand by 2.1× compared to a natural minimum spanning tree heuristic. Our constructed optical trees can improve the timing by about 2× compared to copper trees.