Effect of Load Capacitance and Input Transition Time on FinFET Inverter Capacitances

FinFETs are poised to replace conventional MOSFETs at sub-22-nm technology nodes mainly due to their relatively planar compatible fabrication process. It is well known that FinFET device parasitics are critical for the propagation delay and power dissipation. However, a quantitative understanding of device parasitics for circuit design is yet to be attained. We report a new extension transistor-induced capacitance shielding (ETICS) phenomenon. In this phenomenon, the FinFET extension region forms a transistor, which shields gate-extension fringing field capacitance. Due to this phenomenon, we observe a strong dependence of effective values of FinFET logic gate capacitances on transition times of their terminal voltages, which is unlike the conventional transistors. We show that delay estimation methods need to be modified considering ETICS for efficient FinFET circuit design.