Title :
Efficient architecture for high-speed low-power SC ΣΔ modulators
Author :
Amoroso, F.A. ; Cappuccino, G. ; Pugliese, A.
Author_Institution :
Dept. of Electron., Comput. Sci. & Syst., Univ. of Calabria, Rende, Italy
Abstract :
A new solution to implement efficient switched-capacitor (SC) ΣΔ modulators is presented. The proposed modulator scheme employs an improved SC integrator topology in which voltage buffers are properly introduced. This allows the desired modulator sampling frequency to be obtained by significantly reducing the power consumption with respect to other existing schemes. Design examples of a ΣΔ modulator in a commercial 0.35-μm CMOS technology are reported. Simulation results show that the proposed solution allows a given modulator signal-to-noise and distortion ratio to be achieved by about halving the overall system power consumption.
Keywords :
CMOS integrated circuits; integrated circuit design; low-power electronics; sigma-delta modulation; switched capacitor networks; CMOS technology; SC integrator topology; low-power switched-capacitor ΣΔ modulators; modulator sampling frequency; signal-to-noise and distortion ratio; voltage buffers; CMOS integrated circuits; Capacitance; Frequency modulation; Power demand; Switches; Topology;
Conference_Titel :
Ph.D. Research in Microelectronics and Electronics (PRIME), 2010 Conference on
Conference_Location :
Berlin
Print_ISBN :
978-1-4244-7905-4
