• DocumentCode
    528618
  • Title

    Matrix computation on Connex Parallel Architecture

  • Author

    Calfa, Ana-Maria ; Stefan, Gheorghe

  • Author_Institution
    Fac. of Electron. & Telecommun., Politech. Univ. of Bucharest, Bucharest, Romania
  • fYear
    2010
  • fDate
    7-10 Sept. 2010
  • Firstpage
    375
  • Lastpage
    378
  • Abstract
    The parallel Connex Architecture has specific features imposed in order to improve GIPS/Watt and GIPS/mm2. It is designed for embedded computation in systems on chip design. Its validation supposes exploring by turn different application domains to see how the specific architectural and design assumptions affected the actual performance. In this paper the domain of matrix computation is preliminary investigated.
  • Keywords
    embedded systems; mathematics computing; matrix algebra; parallel architectures; system-on-chip; Connex parallel architecture; embedded computation; matrix computation; systems on chip design; Acceleration; Arrays; HDTV; Parallel architectures; Parallel processing; System-on-a-chip;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Signals and Electronic Systems (ICSES), 2010 International Conference on
  • Conference_Location
    Gliwice
  • Print_ISBN
    978-1-4244-5307-8
  • Electronic_ISBN
    978-83-9047-4-2
  • Type

    conf

  • Filename
    5595168
    • Link To Document
    https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=528618