Broadband quarter-square 4Q analog multiplier based on CMOS inverters

This paper concerns a quarter-square analog 4Q (four-quadrant) multiplier based on own, yet already published, core architecture using four CMOS inverters. An emphasis on control circuits operating at low voltage and highspeed has been put, and therefore the presented circuit solution is suitable for RF applications in communication systems. Operation at high-speed is possible thanks to the architecture containing simple building blocks based on CMOS inverters and using CMOS transistors with sufficiently large biasing currents. Circuit-level design and simulation, circuit layout, post-layout verification for UMC´s 180 um CMOS process has been done on the base Foundry Design Kit in the Cadence DF II environment.