A BPSK/QPSK receiver architecture suitable for low-cost ultra-high rate 60 GHz wireless communications

In this paper, we present a receiver architecture suitable for ultra-high rate wireless communications. The proposed receiver utilizes analog carrier recovery, eliminating the need for very high speed analog to digital converters. We show that the architecture shows excellent phase noise suppression properties, which can further reduce the system cost substantially. The achievable performance of the proposed receiver is investigated via Monte-Carlo simulations using either AWGN channels or measured 60GHz channel data. The corresponding bit-error-rate curves are presented, and the design criteria of an analog implementation are determined and discussed.