• DocumentCode
    53177
  • Title

    Advancing Electronic Packaging Using Microsolder Balls: Making 25-nm Pitch Interconnection Possible

  • Author

    Kyoung-Lim Suk ; Joon Hee Han ; Jeong Yong Lee ; Kyung-Wook Paik

  • Author_Institution
    Dept. of Mater. Sci. & Eng., Korea Adv. Inst. of Sci. & Technol., Daejeon, South Korea
  • Volume
    7
  • Issue
    1
  • fYear
    2013
  • fDate
    Mar-13
  • Firstpage
    24
  • Lastpage
    30
  • Abstract
    Electronic packaging technology has advanced in the direction of integrating diverse components into one package to satisfy market demands for multifunctionality as well as portability. For this reason, various packaging structures have been introduced, such as multichip modules, package on package, package in package, and eventually three-dimensional (3-D)-chip stacks. All of these approaches require increased input/output (I/O) counts, resulting in fine-pitch assembly. Therefore, the most critical issue in current electronic packaging is how to assemble fine-pitch components while avoiding an electrical short circuit in the x-y direction. Much research has been done on fine-pitch interconnecting technology using microsolder balls smaller than 200 nm, but the problems of solder-ball handling and low yield remain. In addition, there have been few reports so far about the fine-pitch interconnection below 25-nm pitch using microsolder balls. Three-dimensional-chip stacks require an additional microsolder and copper hybrid bumping and patterning processes on through silicon via (TSV), which increases the processing cost.
  • Keywords
    fine-pitch technology; integrated circuit interconnections; integrated circuit packaging; microassembling; solders; three-dimensional integrated circuits; 3D-chip stacks; TSV; copper hybrid bumping; electrical short circuit; electronic packaging technology; fine-pitch assembly; fine-pitch interconnecting technology; input-output counts; integrating diverse component direction; microsolder balls; multichip modules; patterning processes; size 25 nm; solder-ball handling problems; three-dimensional chip stacks; three-dimensional-chip stacks; through silicon via; Assembly; Costs; Electronic packaging; Integrated circuit interconnections; Marketing and sales; Nanostructures; Polymers;
  • fLanguage
    English
  • Journal_Title
    Nanotechnology Magazine, IEEE
  • Publisher
    ieee
  • ISSN
    1932-4510
  • Type

    jour

  • DOI
    10.1109/MNANO.2012.2237339
  • Filename
    6461059