• DocumentCode
    533346
  • Title

    Hierarchical verification of chip-level ESD design rules

  • Author

    Lu, Ziyang ; Bell, David Averill

  • Author_Institution
    Mentor Graphics Co., Wilsonville, OR, USA
  • fYear
    2010
  • fDate
    3-8 Oct. 2010
  • Firstpage
    1
  • Lastpage
    6
  • Abstract
    Verification of net-oriented ESD rules is rapidly becoming critical for nanometer design. To meet chip-level complexity and size challenges, a novel approach using topology-aware net types is developed to enable fast, hierarchical verification. This is applied to ESD design rules for power/ground interfaces and successfully adopted in production verification flows.
  • Keywords
    circuit complexity; electrostatic discharge; integrated circuit design; nanoelectronics; chip-level ESD design rules; chip-level complexity; fast hierarchical verification; nanometer design; net-oriented ESD rule verification; power-ground interfaces; production verification flows; topology-aware net types; Algorithm design and analysis; Clamps; Electrostatic discharge; Logic gates; Resistors; Topology; Transistors;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Electrical Overstress/ Electrostatic Discharge Symposium (EOS/ESD), 2010 32nd
  • Conference_Location
    Reno, NV
  • Print_ISBN
    978-1-58537-182-2
  • Electronic_ISBN
    978-1-58537-182-2
  • Type

    conf

  • Filename
    5623713
    • Link To Document
    https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=533346