Improving the ESD self-protection capability of integrated power NLDMOS arrays

Author

Vashchenko, V.A. ; Strachan, A. ; Linten, D. ; Lafonteese, D. ; Concannon, A. ; Scholz, M. ; Thijs, S. ; Jansen, P. ; Hopper, P. ; Groeseneken, G.

Author_Institution

Nat. Semicond. Corp., Santa Clara, CA, USA

fYear

2010

fDate

3-8 Oct. 2010

Firstpage

1

Lastpage

8

Abstract

The self-protection capability (SPC) of integrated power arrays in ESD regimes has been studied for the case of integrated 100 V NLDMOS arrays in a BCD process. A new practical methodology for array comparison has been experimentally validated in order to take into account both gate coupling and avalanche current effects. Using TLP and electrical test methods, two orders of magnitude improvement of SPC has been demonstrated by implementation changes to array design. The effects of the Pbody shading and the drain region design have been quantified and analyzed by numerical simulation, and their physical nature has been discussed.

Keywords

MOS integrated circuits; electrostatic discharge; power integrated circuits; transmission lines; BCD process; ESD self-protection capability; Pbody shading; TLP; avalanche current effects; electrical test methods; gate coupling; integrated power NLDMOS arrays; numerical simulation; voltage 100 V; Arrays; Current measurement; Electrostatic discharge; Fingers; Implants; Logic gates; Transient analysis;

fLanguage

English

Publisher

ieee

Conference_Titel

Electrical Overstress/ Electrostatic Discharge Symposium (EOS/ESD), 2010 32nd

Conference_Location

Reno, NV

Print_ISBN

978-1-58537-182-2

Electronic_ISBN

978-1-58537-182-2

Type

conf

Filename

5623746