• DocumentCode
    533386
  • Title

    ESD protection circuit schemes for DDR3 DQ drivers

  • Author

    Fan, Xiaofeng ; Chaine, Michael

  • Author_Institution
    Micron Technol., Inc., Boise, ID, USA
  • fYear
    2010
  • fDate
    3-8 Oct. 2010
  • Firstpage
    1
  • Lastpage
    6
  • Abstract
    The high-speed interface of DQ pins in DDR3 DRAM requires special ESD considerations. During ESD characterization testing, high voltages from the power rail could pass through the pre-driver PMOSFET to damage the pull-down NMOSFET gate oxide. Special circuit design of the pre-driver circuit is required to eliminate this ESD failure mechanism.
  • Keywords
    DRAM chips; MOSFET; driver circuits; electrostatic discharge; failure analysis; DDR3 DQ drivers; DDR3 DRAM; DQ pins; ESD characterization testing; ESD failure mechanism; ESD protection circuit schemes; high-speed interface; power rail; pre-driver PMOSFET; pull-down NMOSFET gate oxide; special circuit design; Driver circuits; Electric potential; Electrostatic discharge; Logic gates; Pins; Random access memory; Stress;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Electrical Overstress/ Electrostatic Discharge Symposium (EOS/ESD), 2010 32nd
  • Conference_Location
    Reno, NV
  • Print_ISBN
    978-1-58537-182-2
  • Electronic_ISBN
    978-1-58537-182-2
  • Type

    conf

  • Filename
    5623756
    • Link To Document
    https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=533386