DocumentCode :
533387
Title :
CDM effect on a 65nm SOC LNA
Author :
Worley, Eugene R. ; Jalilizeinali, R. ; Dundigal, Sreeker ; Siansuri, Evan ; Chang, Tony ; Mohan, Vivek ; Zhang, Xiaonan
Author_Institution :
Qualcomm, San Diego, CA, USA
fYear :
2010
fDate :
3-8 Oct. 2010
Firstpage :
1
Lastpage :
8
Abstract :
An investigation was performed into the cause of unexpectedly low CDM performance of a 65nm SOC LNA. The main culprit was found to be STI diode overshoot due to the fast CDM current rise time. Solutions included replacing the STI diodes with gated diodes and with incorporating a new type of secondary clamp.
Keywords :
low noise amplifiers; system-on-chip; CDM current rise time; SOC LNA; STI diode overshoot; charged device model; gated diodes; secondary clamp; size 65 nm; Capacitance; Clamps; Discharges; Integrated circuit modeling; Logic gates; Resistors; SPICE;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Electrical Overstress/ Electrostatic Discharge Symposium (EOS/ESD), 2010 32nd
Conference_Location :
Reno, NV
Print_ISBN :
978-1-58537-182-2
Electronic_ISBN :
978-1-58537-182-2
Type :
conf
Filename :
5623757
Link To Document :
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