DocumentCode
533391
Title
Overcoming the unselected pin relay capacitance HBM tester artifact with two pin HBM testing
Author
Ward, Scott ; Burgess, Keith ; Grund, Evan ; Schichl, Joe ; Duvvury, Charvaka ; Koeppen, Peter ; Kunz, Hans
Author_Institution
Texas Instrum., Dallas, TX, USA
fYear
2010
fDate
3-8 Oct. 2010
Firstpage
1
Lastpage
8
Abstract
HBM tester parasitic capacitances are shown to degrade the current pulse rise-times on the ground path return. Rise-times longer than allowed in the HBM specification may cause failures on devices with transiently triggered ESD protection networks. Two pin HBM testing and TLP measurements have verified such failures as being induced by tester parasitics. Updates to the HBM standard are needed to address this testing issue.
Keywords
electrostatic discharge; failure analysis; test equipment; testing; HBM tester parasitic capacitances; TLP measurements; current pulse rise-times degradation; ground path return; pin HBM testing; transient triggered ESD protection networks; unselected pin relay capacitance HBM tester artifact; Capacitance; Clamps; Current measurement; Electrostatic discharge; Pins; Relays; Stress;
fLanguage
English
Publisher
ieee
Conference_Titel
Electrical Overstress/ Electrostatic Discharge Symposium (EOS/ESD), 2010 32nd
Conference_Location
Reno, NV
Print_ISBN
978-1-58537-182-2
Electronic_ISBN
978-1-58537-182-2
Type
conf
Filename
5623762
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