Thermo-sensitive snapback behavioral model intended for electro-thermal simulation of power MOSFETs

It is known that a second breakdown phenomenon similar to that observed in bipolar transistors can occur in power VDMOS, resulting from drain current snapback. A model for the drain current snapback phenomenon and its temperature dependence were investigated up to 300°C involving the avalanche multiplication of the channel current and the activation of the parasitic bipolar transistor. After presenting the theory, this model is compared with TLP (Transmission Line Pulsing) experimental results. Good agreement is achieved between calculated and measured boundaries of the current before and after the snapback has occurred.