Scaling floating-body DRAM: Rationale for a refined 2T Cell

SOI floating-body (IT) DRAM cells (FBCs) are of much interest today mainly because of integration problems associated with the storage capacitor of conventional 1T/1C DRAM in sub-50nm CMOS technology. Two fully depleted (FD) FBCs appear to have the best scaling potential: the planar thin-BOX FD/SOI MOSFET, and the quasi-planar doublegate (DG) FinFET. The authors first examine, via 2-D and 3-D numerical simulations, the scalability of these IT DRAM cells as implied by the memory margin and its dependence on the transistor body (UTB) thickness (t_Si). Then, after showing and explaining significant margin losses in both devices as they are scaled to nanoscale gate lengths (L ), the authors argue that better scalability is achievable in a 2T FBC, or floating-body/gate cell (FBGC), that the authors have previously presented, and describe a novel refinement of the FBGC that yields very long charge/data retention times without undermining the good DRAM performance.