Study on window-scaling algorithm and its FPGA implementation

Traditional bilinear scaling method requires pre-zoom operation while zooming-out an image. In that way, the image resizing system will demand two different scaling sets, one for zooming-out and another for zooming-in, and hence leads to higher cost of hardware implementation and system complication. This paper presents an improved scaling method called window-scaling algorithm. It is relatively low cost and easy to implement. And within the limitation of clock frequency, it could support any mode of display resolution. Basic principle of the proposed algorithm is introduced at first and then scaling effect of different algorithms are compared and analyzed by software. After that, hardware implementation of the algorithm, as well as the general structure is presented in detail. FPGA verification has proved the feasibility and efficiency of the proposed algorithm.