A dynamic scaling length-variable FFT processor

In this paper, architecture of a length variable FFT processor is presented. The processor is based on DIF radix-2/4/8 algorithm and single-path delay feedback architecture. The processor can be configured as 1024, 2048, 4096 and 8192 point processor by connecting and bypassing specific processing elements. To improve processor performance and achieve higher SNR, a dynamic scaling approach is proposed, the internal data is formatted as self defined floating point, and the arithmetic for the self defined floating point is simple. The simulation results show that the dynamic scaling approach can achieve high and constant SNR, and the processor is implemented on FPGA.