Implementation of a fault level meter using a digital signal processing chip

As distributed generation increases within distribution networks, the assessment of potential fault current becomes a more important aspect of network design and planning. Accurate assessment of potential fault current allows provision of appropriate costed connections to new network entrants, and allows continued safe operation of the existing network. Fault level is the product of short circuit current and open circuit voltage. Existing procedures require the use of extensive calculations based on EN60909, and which tend to include a "safety margin" of up to 10%, and/or the use of a commercially available fault level meter that post-processes logged data. This paper will detail the first stage of the development of a fault level meter based on a digital signal processing chip (a Texas Instruments TMS320F2812). The implementation of the calculation of fault contribution caused by the network source impedance in a single-phase system in near real-time, without the need for a separate reference, will be discussed. This is a precursor to the development of a near real-time fault level meter, that will determine both the source impedance and motor (load) contributions to fault level in a three-phase network. The development of a near real-time meter will allow the determination of the temporal profile of network source fault level and quicker and easier monitoring of fault levels, thus reducing the overheads to network operators in planning modifications to the distribution network.