GA-based floorplan-aware topology synthesis of application-specific network-on-chip

Application-specific SoC requires an efficient interconnection topology which does not necessarily conform to regular topologies such as mesh etc. As NoC topology synthesis is an NP-hard problem, we present a genetic-algorithm (GA) based technique to synthesize application-specific NoC topology with system-level floorplan aware. The technique minimizes the power consumption and router resources while satisfying latency and bandwidth performance constraints. We validate our technique by showing the results of several benchmark applications. The proposed technique generates optimal topology within few minutes.