A Low Noise CMOS Phase Locked Loop

Author

Cheng, Mengzhang

Author_Institution

Coll. of Inf. Sci. & Eng., Huaqiao Univ., Quanzhou, China

fYear

2010

fDate

7-9 Nov. 2010

Firstpage

1

Lastpage

4

Abstract

A 5V, 0.6μm CMOS phase locked loop (PLL) is presented. The circuit design of the PLL, which consists of a phase-frequency-detector (PFD), charge-pump (CPP), bias-generator (BG), voltage controlled oscillator (VCO) and differential to single converter (DSC), is introduced and the simulation results are given. The details of design theory and calculation are also described. The PLL is integrated in CMSC 0.6μm 5V 2P2M CMOS technology, the simulation results show that the PLL operates within the frequency range between 100MHz to 500MHz, and the phase noise are -89dBc/Hz and -100dBc/Hz at 100KHz and 1MHz offset frequency.

Keywords

CMOS integrated circuits; charge pump circuits; integrated circuit design; integrated circuit noise; phase convertors; phase locked loops; phase noise; voltage-controlled oscillators; CMOS phase locked loop; CMSC; PLL; bias generator; charge pump; design theory; differential to single converter; frequency 100 MHz to 500 MHz; offset frequency; phase frequency detector; size 0.6 mum; voltage 5 V; voltage controlled oscillator; Charge pumps; Frequency control; Frequency conversion; Phase frequency detector; Phase locked loops; Voltage control; Voltage-controlled oscillators;

fLanguage

English

Publisher

ieee

Conference_Titel

E-Product E-Service and E-Entertainment (ICEEE), 2010 International Conference on

Conference_Location

Henan

Print_ISBN

978-1-4244-7159-1

Type

conf

DOI

10.1109/ICEEE.2010.5660670

Filename

5660670