Title :
Interconnection failure caused by bath degradation in copper electroplating and its VM-FDC using mathematical model
Author :
Imai, Shin-ichi ; Kitabata, Masaki ; Tanaka, Tomoya
Author_Institution :
Manufacturing Technology Center Panasonic Co. Ltd, 800 Higashiyama, Uozu City, Toyama 937-8585, Japan
Abstract :
This paper describes an interconnection failure in a copper damascene process of a system on chip caused by the plating bath degradation in copper electroplating equipment. By “semimetrics” using EES data and a statistical method, it is clarified that the root cause of the failure is the plating bath degradation. The degradation is caused by a by-product, whose existence is confirmed by analyzing the bath plating using HPLC. Therefore, the degradation in the plating bath causes void formation in a via hole. Moreover, a VM model for the bath plating degradation due to the by-product is developed using a mathematical model. VM-FDC using a mathematical model is performed and the interconnection failure is prevented.
Keywords :
Additives; Anodes; Copper; Degradation; Films; Manufacturing; Mathematical model;
Conference_Titel :
Semiconductor Manufacturing (ISSM), 2008 International Symposium on
Conference_Location :
Tokyo, Japan
Electronic_ISBN :
1523-553X