A compact fully-integrated 5.2 – 11.2 GHz low noise amplifier using 0.18-µm CMOS technology

A 5.2 to 11.2 GHz, fully-integrated low noise amplifiers (LNA) was designed and fabricated in the 0.18-μm CMOS technology. This low noise amplifier is a 2-stage design using one cascode RF NMOS configuration with one common source configuration. This device building block preserves high gain, low noise, and good stability without consuming more dc power. By using the proposed circuit topology, the noise from the matching devices can be suppressed. The IC achieves a power gain of 13.9 dB over a 3-dB bandwidth of 5.2 - 11.2 GHz and a noise figure of 4.9 - 6.7 dB. The chip size is only 0.59 × 0.52 mm² and it consumes 8 mW. Still it has good P_1dB performance at the input of -8 dBm and the output with 2 dBm, which is better compared with previously reported CMOS LNAs.