• DocumentCode
    54235
  • Title

    A Variability-Aware Adaptive Test Flow for Test Quality Improvement

  • Author

    Shintani, Michihiro ; Uezono, Takumi ; Takahashi, Tatsuro ; Hatayama, Kazumi ; Aikyo, Takashi ; Masu, Kazuya ; Sato, Takao

  • Author_Institution
    Grad. Sch. of Inf., Kyoto Univ., Kyoto, Japan
  • Volume
    33
  • Issue
    7
  • fYear
    2014
  • fDate
    Jul-14
  • Firstpage
    1056
  • Lastpage
    1066
  • Abstract
    In this paper, we propose a process-variability-aware adaptive test flow that realizes efficient and comprehensive detection of parametric faults. A parametric fault is essentially a malfunction in a large-scale integration chip, which is caused by the variability in fabrication processes. In our adaptive test framework, test pattern sets are altered on individual chips in order to apply the optimal set of test patterns for each chip, and thus the test coverage is improved and the test time is reduced. The test pattern is chosen on the basis of parameter estimations measured using an on-chip sensor with respect to statistical timing information. We also propose a novel metric to quantize the test coverage suitable for evaluating the test quality of parametric faults. Our experimental results using an industrial design show that the proposed flow significantly improves the parametric fault coverage and test efficiency compared to conventional test flows.
  • Keywords
    fault diagnosis; integrated circuit manufacture; integrated circuit testing; large scale integration; parameter estimation; sensors; statistics; adaptive test framework; fabrication processes; industrial design; large-scale integration chip; on-chip sensor; parameter estimations; parametric fault coverage; parametric fault detection; process-variability-aware adaptive test flow; statistical timing information; test coverage; test efficiency; test pattern sets; test quality improvement; Circuit faults; Delays; Large scale integration; Semiconductor device measurement; Testing; Delay variability; parametric faults; path delay test; statistical static timing analysis;
  • fLanguage
    English
  • Journal_Title
    Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on
  • Publisher
    ieee
  • ISSN
    0278-0070
  • Type

    jour

  • DOI
    10.1109/TCAD.2014.2305835
  • Filename
    6835147