A novel source-body biasing technique for RF to DC voltage multipliers in 0.18µm CMOS technology

This paper presents a novel source-body biasing technique for RF to DC voltage multipliers designed in 0.18 μm CMOS Technology for applications where CMOS integration is required. The proposed technique increases voltage gain and efficiency by cancelling body effect and reverse leakage currents. Simulation results using HSPICE software are presented to verify and illustrate the technique by applying it to different topologies tested at different frequencies. Results show that Peak Conversion Efficiencies (PCE) as high as 16.7% can be achieved.