DocumentCode
543938
Title
Performance improvement of block based NAND flash translation layer
Author
Choudhuri, Siddharth ; Givargis, Tony
Author_Institution
Center for Embedded Comput. Syst., Univ. of California, Irvine, CA, USA
fYear
2007
fDate
Sept. 30 2007-Oct. 3 2007
Firstpage
257
Lastpage
262
Abstract
With growing capacities of flash memories, an efficient layer to manage read and write access to flash is required. NFTL is a widely used block based flash translation layer designed to manage NAND flash memories. NFTL is designed to achieve fast write times at the expense of slower read times. While traditionally, it is assumed that the read traffic to secondary storage is insignificant, as reads are cached, we show that this need not be true for NAND flash based storage due to garbage collection and reclamation processes. In this work, we present two independent techniques that extend NFTL and improve the read throughput in particular. The techniques presented add a minimal amount of RAM overhead to a flash controller, while providing, on an average, a 22.9% improvement in page read times and a 2.6% improvements in page write times on a set of file system and rigorous synthetic benchmarks. The techniques presented are well suited for flash controllers that are typically space constrained and have minimal processing power.
Keywords
NAND circuits; benchmark testing; flash memories; performance evaluation; random-access storage; storage management; NAND flash memory; NFTL; block based NAND flash translation layer; file system; flash controller; processing power; read and write access; rigorous synthetic benchmark; Aerospace electronics; Ash; Benchmark testing; Data structures; Flash memory; Performance gain; Random access memory; Block mapping; NAND Flash; Storage;
fLanguage
English
Publisher
ieee
Conference_Titel
Hardware/Software Codesign and System Synthesis (CODES+ISSS), 2007 5th IEEE/ACM/IFIP International Conference on
Conference_Location
Salzburg
Print_ISBN
978-1-5959-3824-4
Type
conf
Filename
5753851
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