DocumentCode
545656
Title
A halting algorithm to determine the existence of decoder
Author
Shen, Sheng Yu ; Qin, Ying ; Zhang, JianMin ; Li, Sikun
Author_Institution
Sch. of Comput. Sci., Nat. Univ. of Defense Technol., Changsha, China
fYear
2010
fDate
20-23 Oct. 2010
Firstpage
91
Lastpage
99
Abstract
Complementary synthesis automatically synthesizes the decoder circuit E-1 of an encoder E. It determines the existence of E-1 by checking the parameterized complementary condition (P C). However, this algorithm will not halt if E-1 does not exist. To solve this problem, we propose a novel halting algorithm to check P C in two steps. First, we over-approximate P C with the linear path unique condition (LP), and then falsify LP by searching for a loop-like path. If such a loop is found, then E-1 does not exist; otherwise, LP can eventually be proved within E´s recurrence diameter. Second, with LP proved above, we construct a list of approximations that forms an onion-ring between PC and LP. The existence of E-1 can be proved by showing that E belongs to all these rings. To illustrate its usefulness, we have run our algorithm on several complex encoder circuits, including PCIE and 10G Ethernet. Experimental results show that our new algorithm always distinguishes correct Es from incorrect ones and halts properly.
Keywords
computability; finite state machines; local area networks; network synthesis; Ethernet; PCIE; complementary synthesis; decoder circuit E-1 existence; halting algorithm; linear path unique condition; loop-like path; onion-ring; parameterized complementary condition; Algorithm design and analysis; Boolean functions; Computational modeling; Decoding; Equations; Registers; Tin; Complementary Synthesis; Halting Algorithm;
fLanguage
English
Publisher
ieee
Conference_Titel
Formal Methods in Computer-Aided Design (FMCAD), 2010
Conference_Location
Lugano
Print_ISBN
978-1-4577-0734-6
Electronic_ISBN
978-0-9835678-0-6
Type
conf
Filename
5770937
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