DocumentCode
548953
Title
ADC limitation analysis for FPGA based digital π/4 DQPSK modem
Author
Timoshenko, Aleksandr ; Pertsev, Leonid
Author_Institution
Telecommun. Syst. Dept., Moscow Inst. of Electron. Technol. (Tech. Univ.), Moscow, Russia
fYear
2011
fDate
16-18 June 2011
Firstpage
1
Lastpage
3
Abstract
This paper present the relationship between the performance of the analog-to-digital converter (ADC) and the digital FPGA and/or IC based π/4 DQPSK. As such, the ADC resolution and the ADC sampling rate are analyzed. As a result, ADC parameters for 20 Mb/s data rate were selected.
Keywords
analogue-digital conversion; differential phase shift keying; field programmable gate arrays; modems; quadrature phase shift keying; ADC limitation analysis; ADC resolution; ADC sampling rate; analog-to-digital converter; digital DQPSK modem; digital FPGA; Bit error rate; Field programmable gate arrays; Modems; Receivers; Signal to noise ratio; Synchronization; Transceivers; π/4 DQPSK; ADC limits; ADC resolution; ADC sampling rate; BER versus SNR; Reed-Solomon code; digital modem; digital transceiver; multimedia communication;
fLanguage
English
Publisher
ieee
Conference_Titel
Systems, Signals and Image Processing (IWSSIP), 2011 18th International Conference on
Conference_Location
Sarajevo
ISSN
2157-8672
Print_ISBN
978-1-4577-0074-3
Type
conf
Filename
5977357
Link To Document