Title :
Restricted moduli Symmetrical quaternary signed-digit addition: A design implementation overview
Author :
Daikpor, Michael Naseimo ; Adegbenro, Oluwole
Author_Institution :
Dept. of Electr. & Electron. Eng., Univ. of Lagos - Akoka, Lagos, Nigeria
Abstract :
In this paper we present an overview of design implementation of a Symmetrical Multiple Valued Logic (SMVL) arithmetic circuit based on the use of restricted moduli Symmetrical Signed Residue Number System (SSRNS). Restricted radix-7 Symmetrical quaternary Signed digit (Rr7SqSd) T-gate based interconnections and full adders are used to implement sign detection, overflow detection and magnitude comparison without recourse to Mixed Radix number System (MRS) converters design or Chinese Remainder Theorem (CRT) computation.
Keywords :
adders; digital arithmetic; integrated circuit interconnections; multivalued logic circuits; Chinese remainder theorem; SMVL arithmetic circuit; T-gate based interconnections; full adders; mixed radix number system converters; overflow detection; restricted moduli; restricted radix-7; sign detection; symmetrical multiple valued logic circuit; symmetrical quaternary signed-digit addition; ymmetrical quaternary signed digit; Adders; Computer architecture; Equations; Generators; Integrated circuit interconnections; Logic gates; Very large scale integration; T-gates; circuit design; full adders; magnitude generator; signed residue;
Conference_Titel :
Systems, Signals and Image Processing (IWSSIP), 2011 18th International Conference on
Conference_Location :
Sarajevo
Print_ISBN :
978-1-4577-0074-3
