DocumentCode
549480
Title
MNFTL: An efficient flash translation layer for MLC NAND flash memory storage systems
Author
Qin, Zhiwei ; Wang, Yi ; Liu, Duo ; Shao, Zili ; Guan, Yong
Author_Institution
Dept. of Comput., Hong Kong Polytech. Univ., Hong Kong, China
fYear
2011
fDate
5-9 June 2011
Firstpage
17
Lastpage
22
Abstract
The new write constraints of multi-level cell (MLC) NAND flash memory make most of the existing flash translation layer (FTL) schemes inefficient or inapplicable. In this paper, we solve several fundamental problems in the design of MLC flash translation layer. The objective is to reduce the garbage collection overhead so as to reduce the average system response time. We make the key observation that the valid page copy is the essential garbage collection overhead. Based on this observation, we propose two approaches, namely, concentrated mapping and postponed reclamation, to effective reduce the valid page copies. We conduct experiments on a set of benchmarks from both the real world and synthetic traces. The experimental results show that our scheme can achieve a significant reduction in the average system response time compared with the previous work.
Keywords
flash memories; logic design; logic gates; storage management; MLC NAND flash memory storage systems; MLC flash translation layer; MNFTL; average system response time reduction; garbage collection overhead reduction; mapping reclamation; multilevel cell flash memory; postponed reclamation; valid page copies reduction; Ash; Benchmark testing; Flash memory; Memory management; Random access memory; System performance; Time factors; Address mapping; Flash translation layer; Garbage collection; MLC NAND flash memory;
fLanguage
English
Publisher
ieee
Conference_Titel
Design Automation Conference (DAC), 2011 48th ACM/EDAC/IEEE
Conference_Location
New York, NY
ISSN
0738-100x
Print_ISBN
978-1-4503-0636-2
Type
conf
Filename
5981700
Link To Document