DocumentCode
549577
Title
An optimal algorithm for layer assignment of bus escape routing on PCBs
Author
Ma, Qiang ; Young, Evangeline F Y ; Wong, Martin D F
Author_Institution
Dept. of Electr. & Comput. Eng., Univ. of Illinois at Urbana-Champaign, Urbana, IL, USA
fYear
2011
fDate
5-9 June 2011
Firstpage
176
Lastpage
181
Abstract
Bus escape routing is a critical problem in modern PCB design. Due to the huge pin count and high density of the pin array, it usually requires multiple layers to route the buses without any conflict. How to assign the escape routing of buses to different layers becomes an important issue. In addition, some buses are required to be assigned on consecutive layers, which adds more difficulties to the layer assignment problem. In this paper, we propose a branch-and-bound based algorithm that optimally solves the layer assignment problem of bus escape routing. Our algorithm guarantees to produce a feasible layer assignment of the buses with a minimum number of layers. We applied our algorithm on industrial data and the experimental results validate our approach.
Keywords
network routing; printed circuit design; PCB design; branch-and-bound; bus escape routing; layer assignment; optimal algorithm; pin array; pin count; Algorithm design and analysis; Arrays; Clocks; Pins; Routing; Search problems; Upper bound; Branch-and-bound; Escape routing; Optimal layer assignment;
fLanguage
English
Publisher
ieee
Conference_Titel
Design Automation Conference (DAC), 2011 48th ACM/EDAC/IEEE
Conference_Location
New York, NY
ISSN
0738-100x
Print_ISBN
978-1-4503-0636-2
Type
conf
Filename
5981933
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