DocumentCode
549588
Title
Temporal isolation on multiprocessing architectures
Author
Bui, Dai ; Lee, Edward ; Liu, Isaac ; Patel, Hiren ; Reineke, Jan
Author_Institution
Univ. of California, Berkeley, CA, USA
fYear
2011
fDate
5-9 June 2011
Firstpage
274
Lastpage
279
Abstract
Multiprocessing architectures provide hardware for executing multiple tasks simultaneously via techniques such as simultaneous multithreading and symmetric multiprocessing. The problem addressed by this paper is that even when tasks that are executing concurrently do not communicate, they may interfere by affecting each others´ timing. For cyberphysical system applications, such interference can nullify many of the advantages offered by parallel hardware and can enormously complicate synthesis of software from models. This paper examines what changes need to be made at lower levels of abstraction to support temporal isolation for effective software synthesis. We discuss techniques at the microarchitecture level, in the memory hierarchy, in on-chip communication, and in the instruction-set architecture that can facilitate temporal isolation.
Keywords
instruction sets; multi-threading; multiprocessing systems; cyberphysical system application; instruction-set architecture; interference; memory hierarchy; microarchitecture level; multiprocessing architecture; on-chip communication; parallel hardware; simultaneous multithreading; software synthesis; symmetric multiprocessing; temporal isolation; Computer architecture; Hardware; Instruction sets; Interference; Random access memory; Real time systems; Timing; PRET machines; Precision-timed architectures; instruction set architecture; memory hierarchy; microarchitecture; network on chip; pipelines;
fLanguage
English
Publisher
ieee
Conference_Titel
Design Automation Conference (DAC), 2011 48th ACM/EDAC/IEEE
Conference_Location
New York, NY
ISSN
0738-100x
Print_ISBN
978-1-4503-0636-2
Type
conf
Filename
5981944
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