DocumentCode :
549589
Title :
Can we go towards true 3-D architectures?
Author :
Gaillardon, Pierre-Emmanuel ; Ben-Jamaa, Haykel ; Morel, Paul-Henry ; Noël, Jean-Philippe ; Clermidy, Fabien ; Connor, Ian O.
Author_Institution :
CEA, LETI, Grenoble, France
fYear :
2011
fDate :
5-9 June 2011
Firstpage :
282
Lastpage :
283
Abstract :
Thanks to recent technology advances, the exploration of the vertical dimension has been shown to be more than a dream for designers. Among those technologies, the vertical transistor has not been exploited yet. This paper describes a novel implementation of logic gates fully benefiting of nanowire-based vertical transistors embedded within the metal lines. The logic design in this technology is explored and its performance is evaluated. A comparison made on an equivalent technology node shows that our cells reduce area and delay by a factor of 31x and 2x respectively. Large reconfigurable logic circuits have been benchmarked showing an improvement of area and delay by 46% and 48% on average.
Keywords :
field effect transistors; integrated circuit design; logic gates; nanowires; three-dimensional integrated circuits; 3D architectures; logic design; logic gates; metal lines; nanowire-based vertical transistors; reconfigurable logic circuits; vertical dimension; CMOS integrated circuits; Delay; Field programmable gate arrays; Logic gates; Metals; Nanowires; Transistors; Back-End; Logic gates; Nanowires;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Design Automation Conference (DAC), 2011 48th ACM/EDAC/IEEE
Conference_Location :
New York, NY
ISSN :
0738-100x
Print_ISBN :
978-1-4503-0636-2
Type :
conf
Filename :
5981945
Link To Document :
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