Orchestrated multi-level information flow analysis to understand SoCs

Complex Systems on Chip are developed by large design teams integrating various different blocks. Typically, no single person in the design team understands all details of such a design. Integrating new designers into the team as well as debugging failures or performance problems becomes a time-consuming cost-generating threat to the overall project. We envision tool support for these critical steps. The paths of information flow are automatically extracted and explanations for certain behavior are derived by reasoning engines. Then, the designer interactively explores the design within this environment.