• DocumentCode
    549622
  • Title

    Leveraging pre-silicon verification resources for the post-silicon validation of the IBM POWER7 processor

  • Author

    Adir, Allon ; Nahir, Amir ; Shurek, Gil ; Ziv, Avi ; Meissner, Charles ; Schumann, John

  • Author_Institution
    IBM Res. - Haifa, Haifa, Israel
  • fYear
    2011
  • fDate
    5-9 June 2011
  • Firstpage
    569
  • Lastpage
    574
  • Abstract
    The growing importance of post-silicon validation in ensuring functional correctness of high-end designs has increased the need for synergy between the pre-silicon verification and post-silicon validation. This synergy starts with a common verification plan. It continues with common verification goals and shared tools and techniques. This paper describes our experience in improving this synergy in the pre- and post-silicon verification of IBM´s POWER7 processor chip and by leveraging pre-silicon methodologies and techniques in the post-silicon validation of the chip.
  • Keywords
    elemental semiconductors; microprocessor chips; silicon; IBM POWER7 processor chip; Si; functional correctness; high-end designs; post-silicon validation; pre-silicon verification resources; synergy; Acceleration; Aging; Complexity theory; Computer bugs; Generators; Observability; Silicon; Coverage; Functional Verification; Post-Silicon Validation; Stimuli Generation;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Design Automation Conference (DAC), 2011 48th ACM/EDAC/IEEE
  • Conference_Location
    New York, NY
  • ISSN
    0738-100x
  • Print_ISBN
    978-1-4503-0636-2
  • Type

    conf

  • Filename
    5981978