Layout effects in fine grain 3D integrated regular microprocessor blocks

Fine grain 3D integration of commonly used components appears to be an attractive architectural solution. But finely partitioned, highly regular blocks face unique layout level challenges due to uneven scaling of Through Silicon Vias (TSVs) and circuit elements. We show that for high yielding TSVs and decreasing transistor sizes, the mismatch between the TSV dimension and the feature size affects the outcome of 3D design space exploration, especially for fine grain partitioned, highly regular microprocessor blocks such as SRAM registers and caches. For a 4-layer implementation of an SRAM register in 45nm technology, we show that improving the TSV yield from 20% to 90% requires layout modifications that worsen register´s performance up to four times. Moreover, the same 4-layer register that performs three times as fast as its single layer equivalent at 20% yield becomes twice slower at 70% yield when layout effects are considered. We also explore some non-conventional physical design schemes for 3D architectural blocks in which performance deterioration is much slower even for very high TSV yields.